mul-add sampling methods

FPGA possesses two main merits:First,it increases multiply-add operation rapidness,resolving real-time disposal.

其主要优点有:用FPGA实现乘加运算,速度非常快,能很好地解决实时处理问题;降低了硬件电路设计的难度,使得非均匀性校正与疵点补偿的整个系统中各个功能之间的配合更简单化。

A new class of codes,derived from single parity check Turbo product code,named product accumulate codes,which are the concatenation of an outer singleparity check Turbo product code and an inner rate1 recursive convolution code is proposed.

对一类性能好且复杂度低的纠错编码技术——乘加码进行了介绍。

This paper develops a high speed complex multiply_adder circuit by using complex programmable logic devices (CPLD).

复数乘加运算是实时数字信号处理系统经常使用的主要运算之一,随着实时数字信号处理的发展,复乘加的运算速度要求越来越高。