combinational logic

Research on power analysis of CMOS combinational logic circuits;

CMOS 组合逻辑[电路]路的功耗分析研究

The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper.

介绍了以Java 2标准中的Applet技术开发组合逻辑[电路]路网络仿真实验平台的原理。

Analysis of trouble diagnosis of combination logic circuit;

组合逻辑[电路]路的故障诊断分析

The Application of Design Combinational Logic Circuits Based on Multisim;

Multisim在组合逻辑[电路]路设计中的应用

Test and diagnosis technology are researched about combinational logic circuits of the control system of magnetic bearings to be used in hard disk drives.

研究了硬盘主轴磁力轴承控制电路中组合逻辑[电路]路的测试及故障诊断方法 ,提出了对芯片级故障 ,固定型故障以及误连等常见故障形式的测试及诊断方

Conventional test generation algorithms for combinational logic circuits make use of backtracking during the search, that results in lowering down their running efficiency.

传统的组合逻辑[电路]路测试方法在搜索过程中都不可避免地要进行反向回溯 ,由于反向回溯的次数过多 ,往往会降低算法的效率 。

This paper addressed the problem of timing safe replaceability for combinational circuits.

讨论了组合逻辑[电路]路的时序安全可替换性问题 ,即如何判断一个组合逻辑[电路]路可以替换另一个组合逻辑[电路]路而电路的速度不会降低 。

Karnaugh map is the most often used and effective tool for the design or analysis of combinatorial logical circuit.

卡诺图是组合逻辑[电路]路设计和分析常用和有效的数学工具,既可以化简逻辑函数,也可以分析组合逻辑[电路]路的竞争冒险。

The paper presents the implementation idea of combinatorial logical circuit based on CPLD in VHDL, and offers a specific application named decoding and I/O control of embedded teaching system to explain how to carry out the idea, including part of programming code.

本文介绍了基于CPLD组合逻辑[电路]路的VHDL设计思想,并结合嵌入式教学系统的译码和I/O控制电路的具体应用,做了较为详细的例证,其中包含部分代码。

The design of combinatorial logical circuit with many output variables is more complex than that with one output variable,because of the more output variables.

大多数的组合逻辑[电路]路属于多输出电路 ,在进行多输出电路的设计时 ,由于输出变量增多 ,情况较单输出电路复杂 ,采用一般的设计方法分别对每个输出函数进行设计 ,尽管各个输出电路是最简的 ,但对整个系统来说并不一定最简 ,这时可以从系统整体来考虑 ,采取利用公共项、利用部分输出结果以获得另一些输出和分解成小系统等方法使系统设计简

Simulation Test on Digital Combined Logic Circuit Based on VB;

利用VB语言设计数字组合逻辑[电路]路仿真实验

This paper introduces the process of establishing simulation model of digital combined logic circuit and the method of carrying out dynamic simulation based on MATLAB.

文章介绍了用MATLAB对数字组合逻辑[电路]路建立完整仿真模型的过程和进行动态仿真的方法,最后给出仿真结果,验证了方法的可行性和模型的正确性。