RTCC Real Time Computer Complex

In this paper a realizing project about IRD is put forward; the technology of source decoding is researched; and the software system of AViA_DMX is designed.

在卫星数字视频广播中 ,综合解码接收机主要的功能模块有 :调谐器、QPSK信道解调、信道前向纠错译码、传送流解复用、音视频解码以及时钟电路、存储器电路和各种接口功能等 。

Research of the Coil Data s Real-Time Reception and Its Database Register System Realized by VC++;

VC++实现的卷材数据实时接收及其数据库记录系统的研究

Embedded Real Time Communication Module in Navigation Receiver;

监测接收机嵌入式实时通信模块设计

Design and Implementation of the Algorithm of Timing Recovery in QAM Receiver;

QAM接收机中定时恢复算法设计和实现

Implement of timing recover algorithm in all-digital receive

全数字接收机定时恢复算法的FPGA实现

Realization of PVT Solution for Single Frequency GPS Software Receiver Based on C++ Platform

单频实时GPS软件接收机导航解算的C++实现

Realization of Wide Instantaneous Dynamic Range in Digital IF Receiver

大瞬时动态范围在数字中频接收机上的实现

Design of High Precison Timekeeping Circuit and Its Realization on the Navigation Receiver;

高精度守时电路设计及其在导航接收机的实现

Design and Implementation of Digital Low-Frequency Time-Code ReceiverBased on FPGA;

基于FPGA的低频时码数字接收机设计与实现

Design and Implementation of Timing Recovery of the Second Generation Digital Satellite Receiver;

第二代数字卫星接收机定时同步的设计与实现

Research on Baseline Surveying Time in GPS Verification

GPS接收机检定中基线测量时间的实验研究

Design of real-time satellite navigation receiver based on standalone DSP platform

基于独立DSP平台的实时卫星导航接收机的设计

This property contains the name of receive port used by the given instance of the receive location. This property is required for instance creation.

此属性包含接收位置的给定实例使用的接收端口的名称。创建实例时要求此属性。

Simultaneously, the receiving machine captures and prints the document.

同时，接收机接收并打印出文件。

About Implement of the Low-frequency Time-code Receiving Via DSP and Research to Improve Timing Precision of the Signal;

低频时码接收的DSP实现以及改进低频定时的研究

The Research and VLSI Implementation of the Receive Module in GPS Receiver;

GPS接收机接收模块的研究与VLSI实现

simultaneous collection of twoion beams

双离子束的同时接收

Timing design of SpaceWire Codec receiver based on FPGA

SpaceWire Codec接收端FPGA时序设计

Signals that a timeout has occurred on a socket read or accept.

标志在套接字读取或接收时出现延时。