folded filter

Its advantage is multi-bank matched filter\'s implementation in the structure of "folded filters + re-order RAM" and its field-programmable gate array(FPGA) implementation in parallel.

为提高捕获速度且减小资源消耗,以"多段匹配滤波器+快速傅里叶变换(FFT)"架构为基础,提出并实现了一种新的适用于高动态下全球定位系统(GPS)P码直捕的时频二维并行搜索算法,其新颖性在于采用"折叠滤波器+重排序随机存取存储器(RAM)"结构实现了多段匹配滤波器,并在现场可编程门阵列(FPGA)中全并行地实现了捕获算法。

Through analyzing operation principle of matched filter and the key parameters which constrain performance of digital matched filter(DMF),an improved folded matched filter architecture is designed on the basis of a folded matched filter provided in reference [5].

本文在分析匹配滤波器的工作原理及制约数字匹配滤波器性能的主要参数后,在文献[5]所给出折叠匹配滤波器的基础上设计了一种改进的折叠匹配滤波器结构,该结构具有更好的可实现性和更少的FPGA资源消耗。